1. Field of the Invention
The present invention generally relates to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit having a logic circuit including storage elements.
2. Discussion of Background
Logic BIST (Built-In Self Test) has become to be widely used in order to avoid increasing tester investments resulting from availability of large-scale and high-performance logic circuits. Logic BIST uses a fault-detecting logic BIST controller installed on a semiconductor integrated circuit chip and enables testing at the same operating frequency (i.e., “at speed”) as for normal operations even on a low-cost tester having low operating frequencies.
Processes of applying logic BIST to logic circuits will be described with reference to the accompanying drawings. FIG. 11 (PRIOR ART) is a circuit configuration diagram showing a conventional logic BIST controller. A configuration of a conventional logic BIST controller is discussed in further detail in “Design for At-speed Test, Diagnosis and Measurement” (Kluwer Academic Publishers, pp. 86-88, 1999).
A logic BIST controller CNTL includes a pattern generator PG to sequentially supply generated test patterns to a user circuit CUT, a signature analyzer SA to check for faults based on a test result acquired from the user circuit CUT, a counter CNT to count the number of generated patterns and check for test completion, a frequency divider DIV to divide a clock signal and supply it to the user circuit, and a control signal generator FSM to control the overall test operation. The user circuit CUT comprises a scan FF with MUX (scan FF) and a combinational circuit CL. The scan FF contains a multiplexer provided before a flip-flop. Each scan FF has two input terminals. One terminal is connected to the combinational circuit CL. The other terminal is connected to an output terminal of the preceding scan FF. A signal path, called a scan path, is formed by connecting between input/output terminals of the scan FFs. The scan path is used to sequentially input test patterns to each scan FF via a scan-in signal line SI and sequentially output test results via a scan-out signal line SO.
A scan enable signal line SE is connected to an input selection terminal of the MUX constituting the scan FF. The scan enable signal line SE is used to control whether the scan FF should select to incorporate a signal from the combinational circuit CL or from the scan path. According to the configuration example in FIG. 11 (PRIOR ART), the user circuit CUT is supplied with clock signals CK1 and CK2 having different frequencies. During a normal operation, selectors SEL1 and SEL2 select and output system clocks CKC0 and CKC2 as the clock signals CK1 and CK2. During a test operation, the selectors SEL1 and SEL2 select and output an output signal CKC3 from a 2-input AND gate and an output signal CKC4 from a frequency divider DIV as the clock signals CK1 and CK2. During BIST execution, the frequency divider DIV supplies the clock signal CK2 mainly because the BIST execution needs to supply a signal resulting from synchronization between the clock signal CK1 and the clock signal CK2.
A delay circuit DY is inserted on a clock signal line connected to the logic BIST controller CNTL. Normally, delays for the clock signals CK1 and CK2 to drive the user circuit are substantially larger than those for the clock signal CKC1 to drive the logic BIST controller CNTL. (Here, a delay means a time interval needed for propagating a signal on a path from an output terminal of an FF transmitting that signal to an input terminal of an FF receiving the signal.) This large difference is because the scale of the user circuit is substantially larger than that of the logic BIST controller, and the user circuit supports a larger clock-related fan-out count than the logic BIST controller. According to the prior art, the delay circuit DY is used to eliminate a delay difference (hereafter referred to as a skew) between clock signals to drive the logic BIST controller CNTL and the user circuit CUT, and both are designed to operate synchronously.
FIG. 12 (PRIOR ART) is a timing chart showing operations of the conventional logic BIST controller. Logic BIST repeats the following operations for the number of test patterns: (1) supplying a test pattern to each scan FF in the user circuit (scan-in operation A); (2) propagating the test pattern to the combinational circuit from each scan FF and incorporating a test result output from the combinational circuit into each scan FF (logic test operation B); and (3) collecting the test result from each scan FF (scan-out C). Logic BIST performs the test operations with respect to all test patterns, and then checks for a fault (fault determination operation D).
The scan-in and scan-out operations are collectively referred to as scan operations. During scan operations, the 2-input AND gate in FIG. 11 (PRIOR ART) partially suppresses transition of the clock signal CK1 for driving the user circuit and decreases the operating frequency (s1401). Since a scan operation consumes power for the entire circuit several times more than that consumed for normal operations, an excess voltage drop may cause incorrect detection of faults, or heat generation may cause chips to be damaged. The clock signal frequency is decreased during scan operations in order to save power consumption for the user circuit and correctly perform the test.
It is necessary to propagate a signal in the logic BIST controller CNTL and the user circuit CUT within a period from a rising edge of a clock signal driving an FF to transmit that signal to a rising edge of a clock signal driving an FF to receive that signal (setup time restriction). For example, a scan enable signal SE1 is propagated between a rising edge of a clock signal CKC1 to drive the transmitting logic BIST controller CNTL and the next rising edge of the clock signal CK1 to drive the receiving user circuit CUT (s1402). Likewise, a clock enable signal En is propagated between a rising edge of the transmitting clock signal CKC1 and the next rising edge of a clock signal CKC0 whose propagation should be inhibited (s1403). When the clock signal CK2 drives the transmitting FF and the clock signal CK1 drives the receiving FF, the signal is propagated between a rising edge of the CK2 and the next rising edge of the CK1 (s1404). In addition, it is necessary to propagate a signal in the logic BIST controller CNTL and the user circuit CUT after a rising edge immediately preceding the most recent rising edge of a clock signal driving the FF to receive that signal (hold time restriction). When the clock signal CK1 drives the transmitting FF and the clock signal CK2 drives the receiving FF, for example, the signal is propagated after a rising edge immediately preceding the most recent one for the CK2 (s1405).
As logic circuits are designed for larger scales and higher performances, however, delays DSE1 and DSE2 of the scan enable signal and delays DCK1 and DCK2 of the clock signal become considerably larger than a clock cycle T. This is because progress towards the large-scale integration increases the number of FFs to be driven by the scan enable signals SE1 and SE2 and clock signals CK1 and CK2, and progress towards the higher performance shortens the clock cycle T. Accordingly, for example, the setup time restriction cannot be satisfied between r1402 and r1404, disabling at-speed logic BIST. As a result, tester investments may increase. In order to satisfy the hold time restriction at r1405, for example, inserting many buffers on the CK1 drive data signal line may increase a chip area.
To solve this problem, there is a proposed a method of dividing the logic circuit and sequentially testing each of the divided logic circuits. This method is discussed in further detail in Proceedings of 11th International VLSI Test Symposium, pp. 4-9, 1993. This method can shorten delays by decreasing the number of FFs simultaneously driven by the scan enable signal and the clock-signal. However, this method extends the time for test (test time) and increases test costs as a result.
Consequently, conventional methods have the problem of applying logic BIST to large-scale and high-performance logic circuits, and thereby disabling an at-speed test or increasing the test time.